 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Myson-Century Technology GENERAL DESCRIPTION CS5820 receives three sets of 7-bit data in CMOS logic level and convert them into three low-voltage differential signaling (LVDS) serial channels. The 7bit input data is referenced to the CKIN signal. The RF pin selects either rising or falling edge trigger of CKIN. Parallel to serial conversion is performed by a 7X internal generated clock reference using on-chip PLL using CKIN. A copy of CKIN but phase-locked to the output serial streams, CLKOUT, is also converted to the fourth LVDS channel. CS5820 offers a reliable communication media using LVDS signaling and provides low EMI dealing with wide, high-speed TTL interfaces. This is especially attractive for interfaces between GUI controller and display systems such as LCD panels for SVGA/XGA/SXGA applications. FEATURES CS5820 21:3 LVDS Transmitter * Three 7-bit serial and one clock LVDS channels. * Compatible with ANSI TIA/EIA-644 LVDS standard. * Wide CKIN ranges from 31MHz to 68MHz. * Fully integrated on-chip PLL that provides 7X CKIN serial shift clock. * Pin selectable for rising or falling edge trigger. * Support power-down mode. * 5V/3.3V tolerant data input. * Single 3.3V supply operation. * CMOS low power consumption. * Functional compatible with DS90C363 and SN75LVDS84. * Available in 48-pin TSSOP package. BLOCK DIAGRAM DIN D0-D6 PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER EN Y0P Y0N SHIFT/LOAD_N CLK DIN D7-D13 PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y1P EN Y1N SHIFT/LOAD_N CLK D14-D20 DIN PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y2P EN Y2N SHIFT/LOAD_N CLK 7xCLK PHASE LOCK LOOP SHIFT/LOAD_N R/F CLK CKOP EN CKON RF CKIN SHTDN CONTROL LOGIC CS5820 Myson-Century Technology, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349 USA: 4020 Moorpark Avenue Suite San Jose, CA, 95117 Tel: 408-243-8388 Fax: 408-243-3188 Sales@myson.com.tw www.myson.com.tw Rev.1.6 October 2001 page 1 of 12 Myson-Century Technology PIN CONNECTION DIAGRAM CS5820 D4 VDD D5 D6 VSS D7 D8 VDD D9 D10 VSS D11 D12 RF D13 D14 VSS D15 D16 D17 VDD D18 D19 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 D3 D2 VSS D1 D0 NC LVDS_VSS Y0N Y0P Y1N Y1P LVDS_VDD LVDS_VSS Y2N Y2P CKON CKOP LVDS_VSS PLL_VSS PLL-VDD PLL_VSS SHTDN CKIN D20 CS5820 36 35 34 33 32 31 30 29 28 27 26 25 Figure-1 48-pin TSSOP page 2 of 12 Myson-Century Technology PIN DESCRIPTION Name D[0-6] D[7-13] D[14-20] CKIN RF I/O I I I I I Description CS5820 Parallel data input for Y0 LVDS channel. D[0] is LSB and D[6] is MSB. MSB is shifted out first. Parallel data input for Y1 LVDS channel. D[7] is LSB and D[13] is MSB. Parallel data input for Y2 LVDS channel. D[14] is LSB and D[20] is MSB. Parallel input clock.This clock signal is used for parallel data reference. It is also used by the on-chip PLL to generate the 7X shift clock for parallel to serial conversion. Rise/fall select. This pin selects the polarity of the CKIN edge for data input. RF = 1 selects CKIN rise edge, and RF = 0 selects CKIN fall edge. Shutdown control (low active). When SHTDN is low, the internal PLL is put into inhibit mode and all LVDS output channels are shut off. This also resets all internal registers. For normal operation, SHTDN should be set to high. Y0 LVDS channel output. These are differential LVDS outputs for Y0 channel corresponds to D[0-6]. Y1 LVDS channel output. These are differential LVDS outputs for Y1 channel corresponds to D[7-13]. Y2 LVDS channel output. These are differential LVDS outputs for Y2 channel corresponds to D[14-21]. Clock LVDS channel output. These are differential LVDS output for the replica of CKIN signal. CKOP and CKON are derived from the internal phase lock loop and phase aligned with the serial data output and can be used by the LVDS receiver for reference edge. Power supply for PLL circuit. Power ground for PLL circuit. Power supply for output buffer circuits. Power ground for output buffer circuits. Power supply for internal circuits. Power ground for internal circuits. SHTDN Y0P, Y0N Y1P, Y1N Y2P, Y2N CKOP, CKON PLL_VDD PLL_VSS LVDS_VDD LVDS_VSS VDD VSS I O O O O P P P P P P page 3 of 12 Myson-Century Technology FUNCTIONAL DESCRIPTION Control logic CS5820 There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are controlled by the control signal "SHTDN". If SHTDN is high, the circuit is in the normal mode, else if low, the circuit is in the power down mode. In the power down mode, every block is off to make sure the least power consumption. 7 x CLK PLL 7 x CLK PLL, which is a phase lock loop, generates seven times clock of CKIN. The signal "RF" indicates that the input data (D0 ~ D20) is rising edge or falling edge trigger by CKIN. If RF=1, it is rigging edge trigger, else if RF=0, it is falling trigger. This seven times clock of CKIN is used by the Parallel ~ LOAD 7 Bit shift Register. 7 x CLK PLL also generate the control signal "SHIFT/LOAD". This signal is also used by the Parallel ~ LOAD 7 Bit Shift Register to indicate when to load data or shift data. Parallel ~ LOAD 7 Bit shift Register This block transfers 7 bits parallel data into one bit series data out. It is controlled by SHIFT/LOAD. If this control signal is low, the data are loaded into shift registers. Next, the SHIFT/LOAD turns high to shift data from shift register to output buffer seven times. One load and then seven shift. Ref: There are two properties in this block. One is that it supports reference voltage to fine the output's common mode voltage. Another is that it generates about (4ns ~6ns) pulse width's power on reset signal. When power on, all block would be reset by power on reset signal to make sure that the circuit would not stuck-at some situation we do not care. Output buffer There are three data output buffers and one clock output buffer. Output buffer generates differential pair output that swing is under 500 ~ 900mV, and common-mode voltage is under 1.125V ~ 1.375V. page 4 of 12 Myson-Century Technology RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL ZL TA Supply voltage High-level input voltage Low-level input voltage Differential load impedance Operating free-air temperature Parameter Min 3 2 90 0 Typ 3.3 Max 3.6 0.8 132 70 CS5820 Unit V V V C TIMING REQUIREMENTS Symbol tC tW tt tsu th Input clock period Pulse duration, high-level input clock Transition time, Input signal Setup time, data, D0~D20 valid before CKIN (RF = 0) or CKIN(RF = 1) Hold time, data, D0~D20 valid after CKIN (RF = 0) or CKIN(RF = 1) 3 1.5 Parameter Min 14.7 0.4tC Typ Max 32.4 0.6tC 5 Unit ns ns ns ns ns page 5 of 12 Myson-Century Technology DC CHARACTERISTICS Symbol VIT VOD VOD VOC(SS) VOC(PP) IIH CS5820 Typ 1.4 340 10 80 40 Max 454 50 1.375 150 20 10 10 24 12 10 250 60 Unit V mV mV V mV A A A mA mA A A mA Parameter Input threshold voltage Differential steady-state output voltage magnitude Change in the steady-state differential output voltage magnitude between opposite binary states Steady-state common-mode output voltage Peak-to-peak common-mode output voltage High-level input current Condition Min - RL = 100 247 1.125 - VIH = VCC - IIH-SHTDN High level input current for SHTDN pin VIH = VCC IIL IOS IOZ ICC(AVG) Low-level input current Short-circuit output current High-impedance output current Quiescent supply current (average) VIL = 0 VO(Yn) = 0 VOD = 0 VO = 0 to VCC Power down SHTDN = 0 Enabled, RL = 100 (4 places) Gray_scale pattern VCC = 3.3V, tC = 15.38ns Enabled, RL = 100 (4 places) Worst_case pattern tC = 15.38ns 50 3 75 mA pF CI Input capacitance Note: All typical values are at VCC = 3.3V, TA = 25C. page 6 of 12 Myson-Century Technology AC CHARACTERISTICS Symbol t0 t1 t2 t3 t4 t5 t6 tskew tc(o) tw tt tenable tdisable CS5820 Typ 0 Parameter CKO to bit 0 CKO to bit 1 CKO to bit 2 CKO to bit 3 CKO to bit 4 CKO to bit 5 CKO to bit 6 Output skew Cycle time, Output clock jitter Pulse duration, high-level output clock Transition time, differential output voltage (tr or tf) Enable time, SHTDN to phase lock (Yn valid) Disable time, SHTDN to off state (CKO low) Condition Tc= 15.38 ns Min -0.2 1/7tc-0.2 2/7tc-0.2 3/7tc-0.2 4/7tc-0.2 5/7tc-0.2 6/7tc-0.2 Max 0.2 1/7tc+0.2 2/7tc+0.2 3/7tc+0.2 4/7tc+0.2 5/7tc+0.2 6/7tc+0.2 Unit ns ns ns ns ns ns ns ns ps ns ps ms ns 100 4/7tc -0.2 260 - 0.2 1500 - 700 1 250 page 7 of 12 Myson-Century Technology tsu tsu CS5820 Dn CKIN (RF=0) CKIN (RF=1) Note: Maximum value of tr, tf = 5ns Figure-2 Setup and Hold Time Definition YP VOD 49.91%(2 Places) VOC YM CL=10pF Max (2 Places) (a) SCHEMATIC 100% VOD(H) VOD(L) tr 80% 0V 20% 0% tf VOC(PP) VOC(SS) VOC(SS) 0V (b) WAVEFORMS Figure-3 Test Load and Voltage Definitions for LVDS Outputs page 8 of 12 Myson-Century Technology TEST PATTERN CS5820 CKIN D0, 6, 12 D1, 7, 13 D2, 8, 14 D3, 9, 15 D18, 19, 20 D4, 5, 10, 11, 16, 17 Figure-4 16-Grayscale Testing Pattern Waveforms CKIN Even Dn Odd Dn Figure-5 The Worst-case Testing Pattern Waveforms CKO t0 Yn t1 t2 t3 t4 t5 t6 Figure-6 Timing Waveform's Definitions page 9 of 12 Myson-Century Technology TYPICAL CHARACTERISTICS CS5820 CKIN SHTDN tenable Yn Invalid valid valid valid Note: RF=1 Figure-7 Enabled Time Waveforms CKIN CKO tdisable SHTDN Note: RF=1 Figure-8 Disabled Time Waveforms page 10 of 12 Myson-Century Technology PACKAGE OUTLINE (48-pin TSSOP) CS5820 D c E1 E L A2 A1 e b A Symbol A A1 A2 b c D E E1 e L Dimensions in Millimeters MIN 1.05 0.05 0.17 0.09 12.40 7.80 6.00 0.50 0 NOM 0.90 0.20 0.15 12.50 8.10 6.10 0.50 MAX 1.20 0.15 0.27 0.20 12.60 8.40 6.20 0.75 7 Dimensions in Inches MIN 0.04 0.002 0.007 0.004 0.488 0.307 0.236 0.020 0 NOM 0.035 0.008 0.006 0.492 0.319 0.240 0.0197 MAX 0.047 0.006 0.010 0.008 0.496 0.330 0.244 0.030 7 page 11 of 12 Myson-Century Technology APPLICATION CIRCUIT SCHEMATICS +3.3V R0_4 JC1 D_CLK 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C1 0.1u R0_1 R0_3 R0_5 C2 0.1u G0_1 G0_3 G0_5 B0_1 B0_3 B0_5 Vs ENA C7 0.1u 1 2 3 JS1 G0_3 G0_4 G0_5 B0_0 B0_1 B0_2 R0_5 G0_0 G0_1 G0_2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IN4 Vcc IN5 IN6 GND IN7 IN8 Vcc IN9 IN10 GND IN11 IN12 R_FB IN13 IN14 GND IN15 IN16 IN17 Vcc IN18 IN19 GND U1 IN3 IN2 GND IN1 IN0 N/C LVDS GND OUT0OUT0+ OUT1OUT1+ LVDS Vcc LVDS GND OUT2OUT2+ CLK OUTCLK OUT+ LVDS GND PLL GND PLL Vcc PLL GND PWR DWN CLK IN IN20 CS5820 R5 10 Hs DIGIT INPUT Vs R6 10 ENA R10 10k R7 10 +3.3V JS2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 R0_3 R0_2 R0_1 R0_0 A0A0+ A1A1+ A2A2+ CLKCLK+ CS5820 +3.3V L1 100uH Hs B0_4 B0_2 B0_0 G0_4 G0_2 G0_0 R0_4 R0_2 R0_0 C4 0.01u C5 0.1u + C3 10u Hi R1 10k Lo B0_3 B0_4 B0_5 +3.3V L2 C8 0.01u C9 0.1u + C6 10u 100uH Hi Lo from Pattern Generator JS3 3 2 1 CLK Sel. 1 2 3 PWR_DN Ext CLK_IN R15 10 +3.3V R16 33 14 JS4 OSC Ext 8 Y1 C14 0.1u JP1 DC+5V 2 + C15 220u C17 0.1u 1 3 1 65MHz 1 7 Int 1 2 3 PWR Sel. U2 VIN VOUT GND 2 + C16 100u C18 0.1u LT1086-3.3/DD Power Adaptor R2 50 R3 82 C10 0.1u R4 50 JC2 LVDS Connector R9 82 A0A1+ A2CLK+ 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 20 19 18 17 16 15 14 26 25 24 23 22 21 20 19 18 17 16 15 14 A0+ A1A2+ CLKR13 82 C12 0.1u R14 50 R17 50 R18 82 C13 0.1u R19 50 CLKCLK+ C11 0.1u R11 50 R12 50 A2A2+ R8 50 A1A1+ A0A0+ Figure-9 Using 48-pin TSSOP package page 12 of 12 |
Price & Availability of CS5820
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |